1. Field of the Invention
The present invention relates to semiconductor devices and semiconductor device manufacturing methods.
2. Description of Related Art
The recent movement toward miniaturization of elements in semiconductor devices and semiconductor integrated circuits has presented the problem of increasing contact resistance. At the same time, many attempts to improve the characteristics of circuit transistors have been made with the use of a technique that intends to increase carrier mobility by applying stress to a channel forming region with a stress applying material.
Concerning the problem of increasing contact resistance, for example, 45 nm High-k+Metal Gate Strain-Enhanced Transistors, C. Auth et al., VLSI Sym. Tech. Dig., pp. 128, (2008) (Non-Patent Document 1) discloses a groove-shaped (trench) contact portion. This publication intends to improve carrier mobility with a contact portion made of a metallic material that has an internal stress.
JP-A-2001-291770 (Patent Document 1) discloses a technique to reduce contact resistance, in which insulating walls are formed on the underlying interlayer insulating layer so as to surround source/drain regions, and a contact plug is formed on a first side-wall spacer provided on the side faces of the insulating walls and a control electrode. Metal plugs connect the contact plug to the wires provided on the overlying interlayer insulating layer formed on the whole surface.